A CMOS (Complementary Metal Oxide Semiconductor) semiconductor device is widely used. The CMOS semiconductor device is provided with insulated gate field effect transistors of different conductivity channel types on a common semiconductor substrate. Gate electrodes of insulated gate field effect transistors of a CMOS semiconductor device need to have desired processed shapes, as development of miniaturization, lower voltage performance and higher integration of the insulated gate field effect transistors.
A method of forming gate electrodes of a CMOS semiconductor device is discloses in Japanese Patent Application Publication (Kokai) No. 11-17024. The CMOS semiconductor device is provided with N-channel and P-channel insulated gate field effect transistors. The N-channel insulated gate field effect transistor is provided with an N+ gate electrode of N+ polycrystalline silicon in which N-type impurities are contained in high concentration. The P-channel insulated gate field effect transistor is provided with a P+ gate electrode of P+ polycrystalline silicon in which P-type impurities are contained in high concentration.
A gate insulating film is formed on a semiconductor substrate to form N-channel and P-channel insulated gate field effect transistors. N+ and P+ polycrystalline silicon films are formed on the gate insulating film. These N+ and P+ polycrystalline silicon films are etched and processed at the same time by RIE (Reactive Ion Etching), for example, using an etching mask, so as to form N+ and P+ gate electrodes.
The gate insulating film under the N+ polycrystalline silicon film may be over-etched or a surface portion of the semiconductor substrate may be scooped out, because the N+ polycrystalline silicon film is etched at an etching rate larger than that of the P+ polycrystalline silicon film. Further, the P+ gate electrode may have a taper shape by the etching process. As a result, it may be difficult to form N+ and P+ gate electrodes with desired vertically-etched shapes at the same time.